Dr Chandrajit Pal
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Email
chandrajit.pal@essex.ac.uk -
Location
Colchester Campus
Profile
Biography
Dr Pal is a Senior Research Officer at the School of Computer Science and Electronic Engineering, University of Essex. In addition, he is a member of the school's Embedded and Intelligent Systems (EIS) Research Group. Before that, he was a National Post-doctoral Fellow (SERB awarded, DST, Govt of India) at IIT Hyderabad, India. He received a PhD in Information Technology from the University of Calcutta. He was awarded the prestigious Presidential DST INSPIRE Fellowship by the Govt of India in 2018 to carry out his doctoral studies. He also worked as a Newton Bhabha Fellow in the School of Electronics and Computer Science department at the University of Southampton, UK in 2016. His research interests mainly include computer vision and signal processing algorithms, custom computing using FPGAs, embedded systems and hardware/software co-design. Besides his interest in intelligent signal processing algorithms, his research also involves developing energy-efficient heterogeneous architectures to execute deep learning techniques on embedded edge devices with limited resources and latency budgets. His research has resulted in over 40 refereed conference and journal papers, patents and book chapters. Before returning to academic research, Dr Pal worked as an AI Research Engineer and Senior Engineer in the semiconductor industry. Presently contributing to an EPSRC project by DSBD named MORELLO-HAT in collaboration with the University of Glasgow and the University of Oxford. BRIEF DESCRIPTION: The CHERI project has created the infrastructure for hardware capabilities. The Morello project implements these concepts and tools for the Arm architecture. In terms of programming languages, the focus of CHERI and Morello has been primarily on C but considerable work has also been done on C++ and some more preliminary work on Rust. The Morello-HAT project (Morello High-Level API and Tooling) intends to create a common API that can be used by compiler developers as well as programmers of higher-level languages, to allow them to leverage Morello's HW capabilities to improve memory security and type safety, spatial as well as temporal, of their language and programs.
Appointments
University of Essex
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Senior Research officer, School of Computer Science and Electronic Engineering, University of Essex (25/8/2023 - present)
Publications
Publications (2)
Pal, C., Chakrabarti, A. and Ghosh, R., (2015). A Brief Survey of Recent Edge-Preserving Smoothing Algorithms on Digital Images
Pal, C., Kotal, A., Samanta, A., Chakrabarti, A. and Ghosh, R., (2014). Design space exploration for image processing architectures on FPGA targets
Journal articles (10)
Pal, C., Pankaj, S., Akram, W., Biswas, D., Mattela, G. and Acharyya, A., (2022). Fragmented Huffman-Based Compression Methodology for CNN Targeting Resource-Constrained Edge Devices. Circuits, Systems, and Signal Processing. 41 (7), 3957-3984
Mattela, G., Tripathi, M. and Pal, C., (2022). A Novel Approach in WiFi CSI-Based Fall Detection. SN Computer Science. 3 (3)
Das, P., Pal, C., Acharyya, A., Chakrabarti, A. and Basu, S., (2021). Deep neural network for automated simultaneous intervertebral disc (IVDs) identification and segmentation of multi-modal MR images. Computer Methods and Programs in Biomedicine. 205, 106074-106074
Sivasubramani, S., Mattela, V., P, R., Pal, C. and Acharyya, A., (2020). Nanomagnetic logic based runtime Reconfigurable area efficient and high speed adder design methodology. Nanotechnology. 31 (18), 18LT02-18LT02
Das, P., Pal, C., Chakrabarti, A., Acharyya, A. and Basu, S., (2020). Adaptive denoising of 3D volumetric MR images using local variance based estimator. Biomedical Signal Processing and Control. 59, 101901-101901
Sivasubramani, S., Mattela, V., Pal, C. and Acharyya, A., (2020). Dipole coupled magnetic quantum-dot cellular automata-based efficient approximate nanomagnetic subtractor and adder design approach. Nanotechnology. 31 (2), 025202-025202
Sivasubramani, S., Mattela, V., Pal, C. and Acharyya, A., (2019). Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate. Nanotechnology. 30 (37), 37LT02-37LT02
Sivasubramani, S., Mattela, V., Pal, C., Islam, MS. and Acharyya, A., (2018). Shape and Positional Anisotropy Based Area Efficient Magnetic Quantum-Dot Cellular Automata Design Methodology for Full Adder Implementation. IEEE Transactions on Nanotechnology. 17 (6), 1303-1307
Pal, C., Das, P., Chakrabarti, A. and Ghosh, R., (2017). Rician noise removal in magnitude MRI images using efficient anisotropic diffusion filtering. International Journal of Imaging Systems and Technology. 27 (3), 248-264
Pal, C., Kotal, A., Samanta, A., Chakrabarti, A. and Ghosh, R., (2016). An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images. International Journal of Reconfigurable Computing. 2016, 1-17
Book chapters (3)
Pal, C. and Acharyya, A., (2022). A Novel Architecture Design for Complex Network Measures of Brain Connectivity Aiding Diagnosis. In: Wearable/Personal Monitoring Devices Present to Future. Springer Singapore. 281- 302. 9789811653230
Pal, C., Vemishetty, N. and Acharyya, A., (2019). Pervasive computing in cardiovascular healthcare. In: Health Monitoring Systems: An Enabling Technology for Patient Care. 177- 211
Acharya, M., Pal, C., Maity, S. and Chakrabarti, A., (2016). Inexact Implementation of Wavelet Transform and Its Performance Evaluation Through Bit Width Reduction. In: Advances in Computing Applications. Springer Singapore. 227- 242. 9789811026294
Conferences (22)
Pal, C., Saha, S., Zhai, X. and McDonald-Maier, KD., (2024). REALITY: RL-PowEred AnomaLy Detection with Imprecise Computing in MulTi-Core SYstems
Zhu, J., Zhu, X., Borowski, M., Zhang, H., Pal, C., Saha, S., Gu, D., McDonald-Maier, KD. and Zhai, X., (2024). NIRVANA: Non-Invasive Real-Time VulnerAbility ANAlysis for RISC-V Processor
Pal, C., Verma, P., Rohit, H., Gyaneshwar, D., Channappayya, SS. and Acharyya, A., (2023). SqueezeNetVLAD: High-speed power and memory efficient GPS less accurate network model for visual place recognition on the edge
Borowski, M., Pal, C., Saha, S., Poli, L., Zhai, X. and McDonald-Maier, K., (2023). Anomaly Behaviour tracing of CHERI-RISC V using Hardware-Software Co-design
Vinay, R., Laad, K., Pal, C., Sasmal, P., Haraki, T., Juyal, C., Elbakri, MAG. and Acharyya, A., (2023). Power and Memory Efficient High-Speed RL Based Run time Power Manager for Edge Computation
Vinay, R., Sasmal, P., Pal, C., Haraki, T., Tamura, K., Juyal, C., Elbakri, MAG., Channappayya, S. and Acharyya, A., (2022). Light Weight RL Based Run Time Power Management Methodology for Edge Devices
Chandrapu, RR., Pal, C., Nimbekar, AT. and Acharyya, A., (2022). SqueezeVGGNet: A Methodology for designing low complexity VGG Architecture for Resource Constraint Edge Applications
Verma, P., Sasmal, P., Pal, C., Channappayya, S. and Acharyya, A., (2022). Clustered Network Adaptation Methodology for the Resource Constrained Platform
Mattela, G., Tripathi, M. and Pal, C., (2021). A novel deep neural design and efficient Pipeline architecture for Person Re-Identification in high resolution Video
Mattela, G., Tripathi, M., Pal, C., Dhiraj, RS. and Acharyya, A., (2020). An Efficient Pipeline for Distant Person Detection and Identification in 4K Video using GPUs
Mattela, G., Pal, C., Tripathi, M., Gavval, R. and Acharyya, A., (2019). Enterprise Class Deep Neural Network Architecture for recognizing objects and faces for surveillance systems
Pal, C., Pankaj, S., Akram, W., Acharyya, A. and Biswas, D., (2018). Modified Huffman based compression methodology for Deep Neural Network Implementation on Resource Constrained Mobile Platforms
Pal, C., Biswas, D., Maharatna, K. and Chakrabarti, A., (2017). Architecture for complex network measures of brain connectivity
Dey, M., Pal, C., Chakrabarti, A. and Ghosh, R., (2016). An efficient hardware accelerated design for image denoising using Extended Trilateral filter
Pal, C., Das, P., Mandal, SB., Chakrabarti, A., Basu, S. and Ghosh, R., (2015). An efficient hardware design of SIFT algorithm using fault tolerant reversible logic
Biswas, T., Pal, C., Mandal, SB. and Chakrabarti, A., (2014). Audio de-noising by spectral subtraction technique implemented on reconfigurable hardware
Das, RK., De, A., Pal, C. and Chakrabarti, A., (2014). DSP hardware design for fingerprint binarization and thinning on FPGA
Ganguly, P., Roy, S., Biswas, T., Pal, C. and Chakrabarti, A., (2014). DSP hardware software co-design of audio de-noising algorithm
Pal, C., Chaudhury, KN., Samanta, A., Chakrabarti, A. and Ghosh, R., (2013). Hardware software co-design of a fast bilateral filter in FPGA
Paul, R., Saha, S., Pal, C. and Sau, S., (2012). Novel architecture of modular exponent on reconfigurable system
Nath, S., Pal, C., Sau, S., Mukherjee, S., Roy, A., Guchhait, A. and Kandar, D., (2012). Design of an FPGA based intelligence traffic light controller with VHDL
Sau, S., Pal, C. and Chakrabarti, A., (2011). Design and implementation of real time secured RS232 link for multiple FPGA communication
Patents (1)
Pal, C., (2017). A system and method for analyzing videos of application or function for feature identification of the videos and related application or function
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